ARM CoreLink CCI-400 Cache Coherent ... - ARM Infocenter
2.11.2. Regulation based on outstanding transactions. The CCI-400 offers an additional mechanism for regulating traffic flows for the benefit of overall ...
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IBM Power 770 and 780 (9117-MMC, 9179-MHC) Technical Overview and ...
2.11.2. EXP24S. SFF. Gen2-bay. Drawer. The EXP24S SFF Gen2-bay Drawer ... the EXP24S are: PCI-X 1.5 GB Cache SAS RAID Adapter 3 Gb (#5904, #5906, ...
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PL310 Cache Controller Technical Reference Manual 2.11.2. Tag RAM
2.11.2. Tag RAM The tag RAM is shown in Figure 2.5 . There is one tag RAM for each way of the L2 cache. A tag RAM is organized as a 23-bit, 22-bit, or 21-bit ...
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PrimeCell Level 2 Cache Controller (PL310 ... - ARM Infocenter
2.11.2. Tag RAM The tag RAM is shown in Figure 2.6 . There is one tag RAM for each way of the L2 cache. A tag RAM is organized as a 23-bit, 22-bit, or 21-bit ...
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